FIGS. 1 and 2 show an exemplary embodiment of an on-chip system. FIG. 2 shows the on-chip system 100 of FIG. 1 in detail. As shown in FIG. 1, the on-chip system 100 includes a transmitter 140 and receiver 180 pair. As shown in FIG. 1, the transmitter 140 receives the data to be transmitted and transmits a high speed serial outgoing data stream. The receiver 180 receives a high speed serial incoming data stream and provides the data to the entire circuit. The high speed serial outgoing data stream and incoming data stream form a high speed serial link.
To enable the receiving end of serial links to receive data reliably, a clock may be embedded into the serial incoming data stream. The receiver 180 recovers the embedded clock from the serial incoming data stream, and uses the recovered clock to strobe the data. Accordingly, clock synchronization associated with parallel data may be improved. During this serialization process, data is usually encoded so that there will be enough signal edges to recover the clock.
As shown in FIG. 2, the transmitter 140 includes a parallel to serial encoder 141, a differential driver 143 and a clock multiplier 145. In the on-chip system of FIG. 2, a system clock is input to the clock multiplier 145, which outputs a bit rate clock to the parallel to serial encoder 141. Parallel data is received at the parallel to serial encoder 141, where data is encoded so that there will be enough signal edges for a receiver to recover this clock. Serial data from the parallel to serial encoder 141 is sent to the differential driver 143 where a differential signal is transmitted therefrom as a serial outgoing data stream.
As shown in FIG. 2, the receiver 180 includes differential sense amplifiers 181 and 187, a buffer 183, a serial to parallel decoder 185, and a phase locked loop 1800. The receiver 180 recovers the clock embedded in the serial incoming data stream input to the receiver 180, and this recovered clock is thus centered in the data eye of the input incoming data stream. That is, using the recovered clock as a strobe, this strobe will latch the data in the incoming data stream and send the data to a serial-to-parallel decoder 185 for use.
As shown in FIG. 2, incoming data streams I and I# with the embedded clock are received by the receiver 180 at the two differential sense amplifiers 181 and 187. One of the differential sense amplifiers 181, along with buffer 183, comprises a data recovery circuit, where data is recovered. As shown in FIG. 2, the differential sense amplifier 181 receives the received data stream with embedded clock I and I#, and outputs differential signals O and O#. Buffer 183 then resolves the differential signals O and O#, or a variation of one of the signals O and O#, as single-ended recovered data to the serial to parallel decoder 185, where the single-ended data is decoded back to parallel data.
As shown in FIG. 2, the other differential sense amplifier 187 receives the incoming data stream with embedded clock I and I#, and converts the data stream to a single-ended wide-swing signal to be sent to the phase locked loop 1800. The differential sense amplifier 187, along with the phase locked loop 1800, comprises a clock recovery circuit, where the phase locked loop 1800 includes a voltage controlled oscillator (VCO) 1802, a divider 1804, a phase detector 1806 and a loop filter 1808. The output of the phase locked loop 1800 is the recovered clock used to strobe the data recovered at the differential sense amplifier 181 of the data recovery circuit.
It should be appreciated that the on chip system 100 shown in FIG. 2 is merely an example of a serial signaling transmit/receive on chip system. That is, there are many exemplary circuit techniques that deliver data from one end of a transmitter to the other end of a receiver, including but not limited to: the use of many bit pairs in lieu of parallel to serial encoding; other forms of encoding beyond 8B/10B encoding, or no encoding at all; the use of recovered clock rather than embedded clock; the use of digital circuit techniques for data/clock recovery other than the use of phase locked loop (PLL); the use of pre-emphasis circuitry to compensate for high frequency loss in transmission media; and the like.
FIG. 3 shows an exemplary diagram of an overlay of the cycles of a data stream. As high speed signals are sent along long circuit traces on a board, backplane or cables, the high speed signals tend to be affected by the properties of the transmission medium and neighboring electrical activities. This will show up as jittering noises and power loss. As shown in FIG. 3, jittering signal edges and varying voltage levels of the data stream form a data eye 200. As the signal is generated over a number of cycles, the signal may vary, and thus, may not be very consistent. That is, at the receiver end, as shown in FIG. 3, the signal may be changed in the time domain and the voltage level domain, forming the data eye.